ICS672-01/02

QUADRACLOCK QUADRATURE DELAY BUFFER

ZERO DELAY BUFFER

IDT™ / ICS™ QUADRACLOCK QUADRATURE DELAY BUFFER

2

ICS672-01/02

REV L 051310

Pin Assignment

Output Clock Mode Select Table

Pin Descriptions

12

1

11

2

10

3

9

ICLK

4

CLK90

5

CLK180

6

FBCLK

7

CLK270

8

VDDIO

CLK0

VDD

GND

GND

S2

GND

S1

16

15

14

13

S0

FBIN

VDD

S2

S1

S0

Output Clocks

0

0

0

Power-down + tri-state

00

1

x1

01

0

x2

01

1

x3

10

0

x4

10

1

x5

11

0

x6

11

1

x0.5

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

ICLK

Input

Clock input.

2

CLK90

Output

Clock output (90° delayed from CLK0).

3

CLK180

Output

Clock output (180° delayed from CLK0).

4

CLK270

Output

Clock output (270° delayed from CLK0).

5

VDDIO

Power

Supply voltage for input and output clocks. Must not exceed VDD.

6, 7, 12

GND

Power

Connect to ground.

8

S0

Input

Select input 0. See table above.

9

S1

Input

Select input 1. See table above.

10

S2

Input

Select input 2. See table above.

11, 13

VDD

Power

Connect to 3.3 V or 5.0 V.

14

CLK0

Output

Clock output phase aligned to ICLK.

15

FBCLK

Output

Feedback clock output (0° phase shift from CLK0).

16

FBIN

Input

Feedback clock input. in normal operation, connect to FBCLK.