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ICS8523I Datasheet(PDF) 17 Page - Renesas Technology Corp |
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ICS8523I Datasheet(HTML) 17 Page - Renesas Technology Corp |
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17 / 19 page ![]() ICS8523CGI REVISION E NOVEMBER 15, 2012 17 ©2012 Integrated Device Technology, Inc. ICS8523I Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change Date B T5 5 AC Characteristics table - tPD row, changed Min. from 1.2ns to 1.0ns. 1/11/02 B 1 Revised Features section, Bullet 1,6 - took out 1.8V 5/6/02 B 8 - 10 In the Application Information section, added Schematic Examples. 10/28/02 C T2 T4D 2 4 5 11 - 12 Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. HSTL DC Characteristics Table - changed VOH 1V min. to 0.9V min. Power Considerations - changed Total Power Dissipation to reflect VOH change. Calculations changed due to new Total Power Dissipation. Changed LVHSTL to HSTL throughout data sheet. 6/23/03 C T9 1 9 15 Features section - added Lead-Free bullet. Updated LVPECL Clock Input Interface section. Added Lead-Free marking to Ordering Information table. 9/13/04 C T8 15 Ordering Information Table - in the Part/Order Number and Marking columns, changed die revision from “B” to “C”. 3/2/07 D T5 6 AC Characteristics Table - changed tR/tF minimum from 300ps to 250ps. 3/13/07 E T4C T4D T5 T9 1 4 4 5 5 6 8 8 9 10 11 16 Features Section - added Additive Phase Jitter bullets. Pin Assignment has nCLK, nPCLK. Changed CLK, PCLK to nCLK, nPCLK throughout the datasheet. Absolute Maximum Ratings - corrected Outputs Rating. Differential DC Characteristics Table - updated notes. LVPECL DC Characteristics Table - updated notes. AC Characteristics Table - added Buffer Additive Phase Jitter specs. Add thermal note and updated NOTE 4. Added Additive Phase Jitter plot. Corrected Output Duty Cycle/Pulse Width/Period diagram. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Updated 3.3V Differential Clock Input Interface application note. Updated 3.3V LVPECL Clock Input Interface application note. Added HSTL Output Termination diagram. Ordering Information Table - corrected marking. 1/21/11 E T9 16 Removed leaded orderable parts from Ordering Information table 11/15/12 |
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