ICS853S12I datasheet(10/18 Pages) RENESAS

10 / 18 page

IDT™ / ICS™ LVPECL FANOUT BUFFER

ICS853S12AKI REV. A MAY 21, 2008

ICS853S12I

LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are rec-

ommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminat-

ing resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion.

Figures 4A and 4B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FIGURE 4B. LVPECL OUTPUT TERMINATION

FIGURE 4A. LVPECL OUTPUT TERMINATION

TERMINATION FOR 3.3V LVPECL OUTPUTS

ICS853S12I Datasheet(PDF) 10 Page - Renesas Technology Corp