6

AV9110

Figure 1 - Serial Programming

AC Timing

Frequency Acquisition Time

Frequency acquisition (or “lock”) time is the time that it

takes to change from one frequency to another, and is a

function of the difference between the old and new

frequencies. The AV9 11 0 can typically lock to within 1% of

a new frequency in less than 200 microseconds. This is also

true with power-on.

Power-On Reset

Upon power-up the internal latches are preset to provide the

following output clock frequencies (14.318 MHz reference

assumed):

Device

CLK output

CLK/X output

AV9110-01

25.175 MHz

6.29 MHz

AV9110-02

25.175 MHz

12.59 MHz

These preset default frequencies can be changed with a custom

metal mask, as can other attributes.

The actual numbers of these output clock frequencies

(14.318MHz reference assumed) are:

Device

CLK output

CLK/X output

AV9110-01

25.255 MHz

6.31 MHz

AV9110-02

25.255 MHz

12.63 MHz

and these are within 0.32%.

Jitter

For high performance applications, the AV9110 offers ex-

tremely low jitter and excellent power supply rejection. The

one sigma jitter distribution is typically less than ±125ps.

For optimum performance, the device should be decoupled

with both a 2.2mF and a 0.1mF capacitor. Refer to

Recommended Board Layout diagram on page 8.

Output Enable

The AV9110 outputs can be disabled with either the OE pin

or through serial programming. Setting the OE pin low tristates

CLK and CLK/X. Alternatively, setting bits D19 and D20

low in the serial word will tristate the two outputs. Both the

OE pin and D19 or D20 must be high to enable an output.

Frequency Transition Glitches

The AV9110 starts changing frequency on the rising edge of

the 24th serial clock. If the programming of any output

divider is changed, the output clock may glitch before locking

to the new frequency in less than 200µs with no output

glitches (no partial clock cycles).

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