ADF4108BCPZ datasheet(7/20 Pages) AD

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ADF4108

Rev. 0 | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RSET

CPGND

AGND

RFINB

RFINA

AVDD

REFIN

MUXOUT

DATA

CLK

DGND

DVDD

TOP VIEW

(Not to Scale)

ADF4108

NOTE: TRANSISTOR COUNT 6425 (CMOS),

303 (BIPOLAR).

15 MUXOUT

14 LE

13 DATA

12 CLK

CPGND 1

AGND 2

AGND 3

11 CE

RFINB 4

RFINA 5

PIN 1

INDICATOR

TOP VIEW

(Not to Scale)

ADF4108

Figure 3. TSSOP Pin Configuration for TSSOP

Figure 4. LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

TSSOP

LFCSP_VQ

Mnemonic

Description

RSET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.

The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is

SET

MAX

with RSET = 5.1 kΩ, ICP MAX = 5 mA.

Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn

drives the external VCO.

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

2, 3

AGND

Analog Ground. This is the ground return path of the prescaler.

RFINB

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF. See Figure 12.

RFINA

Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

6, 7

AVDD

Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the

analog ground plane should be placed as close as possible to this pin. AVDD must be the same value

as DVDD.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input

resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or

it can be ac-coupled.

9, 10

DGND

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into

three-state mode. Taking the pin high will power up the device, depending on the status of the

power-down bit, F2.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS

input.

DATA

Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input

is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches, the latch being selected using the control bits.

MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

16, 17

DVDD

Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.

Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where

VDD is 3.3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.

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