| Electronic Components Datasheet Search |
|
STM32H7 Datasheet(PDF) 26 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32H7 Datasheet(HTML) 26 Page - STMicroelectronics |
|
26 / 357 page ![]() Functional overview STM32H742xI/G STM32H743xI/G 26/357 DS12110 Rev 10 3.3 Memories 3.3.1 Embedded flash memory The STM32H742xI/G and STM32H743xI/G devices embed up to 2 Mbytes of flash memory that can be used for storing programs and data. The flash memory is organized as 266-bit flash words memory that can be used for storing both code and data constants. Each word consists of: • One flash word (8 words, 32 bytes or 256 bits) • 10 ECC bits. The flash memory is divided into two independent banks. Each bank is organized as follows: • A user flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI) containing eight user sectors of 128 Kbytes (4 K flash memory words) • 128 Kbytes of System flash memory from which the device can boot • 2 Kbytes (64 flash words) of user option bytes for user configuration 3.3.2 Embedded SRAM All devices feature: • 384 (STM32H742xI/G) or 512 Kbytes (STM32H743xI/G) of AXI-SRAM mapped onto AXI bus on D1 domain. • SRAM1 mapped on D2 domain: 32 (STM32H742xI/G) or 128 Kbytes (STM32H743xI/G) • SRAM2 mapped on D2 domain: 16 (STM32H742xI/G) or 128 Kbytes (STM32H743xI/G)128 Kbytes • SRAM3 mapped on D2 domain: 32 Kbytes (STM32H743xI/G only) • SRAM4 mapped on D3 domain: 64 Kbytes • 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. • RAM mapped to TCM interface (ITCM and DTCM): Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the CPU(AHBP): – 64 Kbytes of ITCM-RAM (instruction RAM) This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU. – 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports) The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex®-M7 dual issue capability. The MDMA can be used to load code or data in ITCM or DTCM RAMs. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |