AM70PDL129CDH datasheet(78/127 Pages) SPANSION

Part #	AM70PDL129CDH

Description	Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)

PDF	127 Pages

Scroll/Zoom	100%

Manufacturer	SPANSION [SPANSION]

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Am70PDL127CDH/Am70PDL129CDH

November 24, 2003

ADV ANCE

I N FO RMAT I O N

TIMING DIAGRAMS

Figure 26.

Timing Waveform of Read Cycle 1

Figure 27.

Timing Waveform of Read Cycle 2

Notes:

1. t

HZ and tOZ are defined as the time at which the outputs

achieve the open circuit conditions and are not

referenced to output voltage levels.

2. At any given temperature and voltage condition, t

HZ (Max) is

less than t

LZ (Min) both for a given device and from device

interconnection.

3. t

OE (Max) is met only when OE# becomes enabled after tAA

(Max).

4. If invalid address signals shorter than min. t

RC are

continuously repeated for over 4 us, the device needs a

normal read timing (t

RC) or needs to sustain standby state

for min. t

RC at least once in every 4 us.

Address

Data Out

Previous Data Valid

Data Valid

tAA

tRC

tOH

Data Valid

High-Z

tRC

tOH

tAA

tBA

tOE

tOLZ

t BLZ

t LZ

t OHZ

t BHZ

t HZ

tCO

Address

CS#1s

UB#, LB#

OE#

Data out

AM70PDL129CDH Datasheet(PDF) 78 Page - SPANSION

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