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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 25

The device is controlled and monitored by registers accessed through the I²C serial interface. These

registers provide device control functions and can be read to determine device status and acquire

device data.

The register set is summarized below. The values of all registers and fields that are listed as reserved

or are not listed must not be changed at any time. Two-byte fields are always latched with the low byte

followed by the high byte. The

“Name” column illustrates the purpose of each register by highlighting

the function associated to each bit. The bits are shown from MSB (D7) to LSB (D0). GRAY fields are

reserved and their values must not be changed at any time.

In order to access registers from 0x60 to 0x74 bit REG_BANK in register CFG0 (0xA9) needs to be

set to “1”.

10.1

Figure 32:

Addr

Name

<D7>

<D6>

<D5>

<D4>

<D3>

<D2>

<D1>

<D0>

0x60

ASTATUS

ASAT_

STATUS

AGAIN_STATUS [3:0]

0x61

CH0_DATA

CH0_DATA_L [7:0]

0x62

CH0_DATA_H [7:0]

0x63

ITIME

ITIME_L [7:0]

0x64

ITIME_M [7:0]

0x65

ITIME_H [7:0]

0x66

CH1_DATA

CH1_DATA_L [7:0]

0x67

CH1_DATA_H [7:0]

0x68

CH2_DATA

CH2_DATA_L [7:0]

0x69

CH2_DATA_H [7:0]

0x6A

CH3_DATA

CH3_DATA_L [7:0]

0x6B

CH3_DATA_H [7:0]

0x6C

CH4_DATA

CH4_DATA_L [7:0]

0x6D

CH4_DATA_H [7:0]

0x6E

CH5_DATA

CH5_DATA_L [7:0]

0x6F

CH5_DATA_H [7:0]

0x70

CONFIG

LED_SEL

INT_SEL

INT_MODE[1:0]

0x71

STAT

WAIT_SYNC

READY

0x72

EDGE

SYNC_EDGE [7:0]

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