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MF-2500DS-R14-200 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part # MF-2500DS-R14-200
Description  SONET/SDH TRANSMITTER & RECIEVER
PDF  9 Pages
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MF-2500DS-R14-200 Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI (OPTICAL DEVICES)
MF-2500DS-T12-18x/19x/20x/21x
MF-2500DS-R13-18x
MF-2500DS-R14-19x/20x/21x
SONET/SDH TRANSMITTER & RECIEVER
ELECTRICAL/OPTICAL CHARACTERISTICS (TLD=25
°C, unless otherwise noted)
All parameters are specified over the operating case temperature.
Measurement conditions are at 2488.32Mb/s +/-20ppm, NRZ PN2
23-1 and 50% duty cycle data signal.
Vcc=+5.0V+/-5%, Vee=-5.2V+/-5%, and for Transmitter.
note : Vcc-Vee ; with Vcc at +5V Vee must be at 0V ; with Vee at -5.5V Vcc must be at 0V
note : Internally AC coupled with 50ohm internal termination
Transmitter
class1 : -5
°C to +75°C class2 : -40°C to +85°C
Parameters
Condition
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
note 1
-
4.75
5.0
5.5
V
Power consumption
total
-
-
0.8
2.0
W
Input sensitivity data and clock voltage
note 2,3
SV
0.6
0.8
1.0
Vpp
Normalized back face voltage
note 5
-
-
500
-
mV
Monitor bias voltage
note 5
-
-
20
-
mV/mA
Logic level
note 4
-
TTL compatible
-
note 1: Vcc-Vee ; with Vcc at +5V Vee must be at 0V ; with Vee at -5.5V Vcc must be at 0V
note 2: Internally AC coupled with 50ohm internal termination
note 3: This sensitivity is achieved by applying at minimum either a 0.6Vpp signal on one input while
the other input is tied to ground or by applying two complementary 0.3Vpp signal on both inputs.
note 4: when Vcc at +5V and Vee at 0V
note 5: This voltage is measured taking Vee as reference.
Receiver
class1 : -5
°C to +75°C class2 : -40°C to +85°C
Parameters
Condition
Symbol
Min.
Typ.
Max.
Unit
Positive supply voltage
-
4.75
5.0
5.25
V
Negative supply voltage
if equired
-
-5.5
-5.2
-4.94
V
Power consumption
total
-
-
1.3
3
W
Output data and clock voltage single ended
SV
0.3
0.4
1
Vpp
Output data and clock voltage differential
DV
0.6
0.8
2
Vpp
Jitter generation
GR-253/ITU-T G958
Ulrms
Jitter tolerance
GR-253/ITU-T G958
Ulpp
Jitter transfer peaking
-
GR-253/ITU
dB
Logic output level
note 6
-
TTL compatible
-
note 6: At the moment the jitter bandwidth performance according GR-253/ITU-T G958 is not met atthe receiver interface level.
Additional clock filtering is supposed to be done at lower data rates.
Jitter transfer bandwidth will be defined at this level which is a parameter of the whole network element and not of the
receiver element.
A further version is under investigation to met simultaneously all the GR-253/ITU-T G958 jitter specifications at the
physical interface level.



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