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STM32L151C6U6ADTR Datasheet(PDF) 101 Page - STMicroelectronics

Part # STM32L151C6U6ADTR
Description  Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,128KB Flash, 32KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
PDF  130 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L151C6U6ADTR Datasheet(HTML) 101 Page - STMicroelectronics

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DocID024330 Rev 5
101/130
STM32L151x6/8/B-A STM32L152x6/8/B-A
Electrical characteristics
105
dOffset/dT(1)
Offset error temperature
coefficient (code 0x800)
VDDA = 3.3V,VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer OFF
-20
-10
0
µV/°C
VDDA = 3.3V, VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer ON
020
50
Gain(1)
Gain error(6)
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
+0.1 /
-0.2%
+0.2 / -
0.5%
%
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
+0 / -
0.2%
+0 / -
0.4%
dGain/dT(1)
Gain error temperature
coefficient
VDDA = 3.3V, VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer OFF
-10
-2
0
µV/°C
VDDA = 3.3V, VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer ON
-40
-8
0
TUE(1)
Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-12
30
LSB
No RL, CL ≤ 50 pF
DAC output buffer OFF
-8
12
tSETTLING
Settling time (full scale: for a
12-bit code transition
between the lowest and the
highest input codes till
DAC_OUT reaches final
value ±1LSB
CL ≤ 50 pF, RL ≥ 5 kΩ
-7
12
µs
Update rate
Max frequency for a correct
DAC_OUT change (95% of
final value) with 1 LSB
variation in the input code
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
tWAKEUP
Wakeup time from off state
(setting the ENx bit in the
DAC Control register)(7)
CL ≤ 50 pF, RL ≥ 5 kΩ
-9
15
µs
PSRR+
VDDA supply rejection ratio
(static DC measurement)
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-60
-35
dB
1. Guaranteed by characterization results.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code
4095.
4. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
7. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Table 58. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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