ICS841484I Data Sheet

FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR

ICS841484DKI REVISION A NOVEMBER 7, 2012

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©2012 Integrated Device Technology, Inc.

NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential

cross points.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Please refer to the Phase Noise Plots.

NOTE 4: Measurement taken from single-ended waveform.

NOTE 5: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.

NOTE 6: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.

NOTE 7: Measurement taken from a differential waveform.

NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is

allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.

NOTE 9: Spread Spectrum clocking enabled.

NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

See Parameter Measurement Information Section.

NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement. See Parameter Measurement Information Section.

NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the

VCROSS for any particular system. See Parameter Measurement Information Section.

NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

See Parameter Measurement Information Section.

NOTE 14: REF_OUT duty cycle characterized with REF_IN input duty cycle between 48% and 52%.