6

Integrated

Circuit

Systems, Inc.

ICS950220

0467G—03/02/07

Byte 1: Output Control Register

(1 = enable, 0 = disable)

Byte 3: Output Control Register

(1 = enable, 0 = disable)

Byte 2: Output Control Register

(1 = enable, 0 = disable)

Byte 4: Output Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B9

3

,

0

41

2

C

/

T

U

P

C

6

t

i

B3

4

,

4

41

1

C

/

T

U

P

C

5

t

i

B6

4

,

7

41

0

C

/

T

U

P

C

4

t

i

B-

X

k

c

a

b

d

a

e

R

4

S

F

3

t

i

B-

X

k

c

a

b

d

a

e

R

3

S

F

2

t

i

B-

X

k

c

a

b

d

a

e

R

2

S

F

1

t

i

B-

X

k

c

a

b

d

a

e

R

1

S

F

0

t

i

B-

X

k

c

a

b

d

a

e

R

0

S

F

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

1

t

i

b

l

o

r

t

n

o

c

6

6

V

3

.

c

n

y

s

A

U

P

C

h

t

i

w

s

u

o

n

o

r

h

c

n

y

s

a

z

H

M

2

3

/

4

6

=

I

C

P

/

6

6

V

3

:

0

U

P

C

h

t

i

w

s

u

o

n

o

r

h

c

n

y

s

z

H

M

3

.

3

3

/

6

.

6

6

=

I

C

P

/

6

6

V

3

:

1

6

t

i

B-

X

d

e

v

r

e

s

e

R

5

t

i

B-

X

d

e

v

r

e

s

e

R

4

t

i

B1

31

#

Z

H

M

8

4

_

4

2

/

0

_

6

6

V

3

3

t

i

B-

X

d

e

v

r

e

s

e

R

2

t

i

B2

21

3

_

6

6

V

3

1

t

i

B1

21

2

_

6

6

V

3

0

t

i

B0

21

1

_

6

6

V

3

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

L

E

S

T

L

U

M

6

t

i

B7

11

6

_

K

L

C

I

C

P

5

t

i

B6

11

5

_

K

L

C

I

C

P

4

t

i

B5

11

4

_

K

L

C

I

C

P

3

t

i

B2

11

3

_

K

L

C

I

C

P

2

t

i

B1

11

2

_

K

L

C

I

C

P

1

t

i

B0

11

1

_

K

L

C

I

C

P

0

t

i

B9

1

0

_

K

L

C

I

C

P

Notes:

1. PWD = Power on Default

2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at

high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B4

31

T

O

D

_

Z

H

M

8

4

6

t

i

B5

31

B

S

U

_

z

H

M

8

4

5

t

i

B-

1

e

l

b

a

s

i

D

=

0

,

e

l

b

a

n

E

=

1

t

c

e

t

e

d

t

f

i

h

s

r

a

e

g

t

e

s

e

R

4

t

i

B-

X

d

e

v

r

e

s

e

R

3

t

i

B1

30

,

#

Z

H

M

8

4

_

4

2

/

0

_

6

6

V

3#

Z

H

M

8

4

_

4

2

=

0

,

z

H

M

6

6

.

6

6

=

1

)

t

l

u

a

f

e

d

(

2

t

i

B-

X

d

e

v

r

e

s

e

R

1

t

i

B6

1

8

K

L

C

I

C

P

0

t

i

B5

1

7

K

L

C

I

C

P