723623L15PFG8 datasheet(13/29 Pages) RENESAS

13 / 29 page

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW

if a word in memory is the next data to be sent to the FlFO output register and

twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince

thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil

thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing

the Empty Flag HIGH; only then can data be read.

ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing

clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs

attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 10 and 11).

FULL/INPUT READY FLAGS (FF/IR)

Thisisadualpurposeflag. InFWFTmode,theInputReady(IR)function

isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For

bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation

isfreeintheFIFOtoreceivenewdata.Nomemorylocationsarefreewhenthe

Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.

TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat

writesdatatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,each

timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine

that controls a Full/Input Ready flag monitors a write pointer and read pointer

comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.

FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready

to be written to in a minimum of two cycles of the Full/Input Ready flag

synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo

cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe

nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition

ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input

Ready flag HIGH.

ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock

beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime

tSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcyclecanbe

the first synchronization cycle (see Figures 13 and 14).

ALMOST-EMPTY FLAG (AE)

TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads

datafromitsarray(CLKB).ThestatemachinethatcontrolsanAlmost-Emptyflag

monitors a write pointer and read pointer comparator that indicates when the

FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.The

Almost-EmptystateisdefinedbythecontentsofregisterX.Theseregistersare

loaded with preset values during a FIFO reset, programmed from Port A, or

programmedserially(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogram-

mingsection). AnAlmost-EmptyflagisLOWwhenitsFIFOcontainsXorless

words and is HIGH when its FIFO contains (X+1) or more words. Note that a

data word present in the FIFO output register has been read from memory.

TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock

arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel

offill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords

remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe

writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH

bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO

writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost-

Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs

at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.

Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-

nization cycle. (See Figure 15).

ALMOST-FULL FLAG (AF)

TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites

datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa

writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory

statusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstateisdefined

by the contents of register Y. These registers are loaded with preset values

duringaFlFOresetor,programmedfromPortA,orprogrammedserially(see

Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost-

FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthanorequal

to(256-Y),(512-Y),or(1,024-Y)fortheIDT723623,IDT723633,orIDT723643

respectively. AnAlmost-FullflagisHIGHwhenthenumberofwordsinitsFIFO

is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the

IDT723623, IDT723633, or IDT723643 respectively. Note that a data word

present in the FIFO output register has been read from memory.

TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock

arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof

fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]

or less words remains LOW if two cycles of its synchronizing clock have not

elapsed since the read that reduced the number of words in memory to [256/

512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH

transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber

ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan

Almost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifit

occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords

inmemoryto[256/512/1024-(Y+1)]. Otherwise,thesubsequentsynchronizing

clock cycle may be the first synchronization cycle. (See Figure 16).

MAILBOX REGISTERS

Two 36-bit bypass registers are on the IDT723623/723633/723643 to

passcommandandcontrolinformationbetweenPortAandPortBwithoutputting

it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail

registerandaFIFOforaportdatatransferoperation.Theusablewidthofboth

the Mail1 and Mail2 registers matches the selected bus size for Port B.

ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen

aPortAwriteisselectedbyCSA,W/RA,andENAwithMBAHIGH. Iftheselected

Port B bus size is 36 bits, the usable width of the Mail1 register employs data

linesA0-A35. IftheselectedPortBbussizeis18bits,thentheusablewidthof

theMail1RegisteremploysdatalinesA0-A17.(Inthiscase,A18-A35aredon’t

careinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidthofthe

Mail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’tcare

inputs.)

A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2

HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2

employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the

usablewidthoftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,B18-

B35aredon’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusable

widthoftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,B9-B35are

don’tcareinputs.)

Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)

LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.

Whendataoutputsofaportareactive,thedataonthebuscomesfromthe

FIFO output register when the port Mailbox Select input is LOW and from the

mail register when the port Mailbox Select input is HIGH.

TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition

on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB

723623L15PFG8 Datasheet(PDF) 13 Page - Renesas Technology Corp

723623L15PFG8 Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL