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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

The system logic TAP controller transitions from state to state, according to the value present on TMS, as sampled on the rising edge of TCK. The

Test-Logic Reset state can be reached either by asserting TRST or by applying a 1 to TMS for five consecutive cycles of TCK. A state diagram for the

TAP controller appears in Figure 5.2. The value next to state represent the value that must be applied to TMS on the next rising edge of TCK, to tran-

sition in the direction of the associated arrow.

Figure 20 State Diagram of the TAP Controller

Test Data Register (DR)

The Test Data register contains the following:

u

The Bypass register

u

The Boundary Scan registers

u

The Device ID register

These registers are connected in parallel between a common serial input and a common serial data output, and are described in the following

sections. For more detailed descriptions, refer to IEEE Standard Test Access port (IEEE Std. 1149.1-1990).

Boundary Scan Registers

The CPS-10Q boundary scan chain is 142 bits long. The five JTAG pins do not have scan elements associated with them. Full boundary scan details

can be found in the associated BSDL file which may be found on our web site (www.IDT.com). The boundary scan chain is connected between TDI

and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes through the

UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output latches is immediately transferred to the corresponding

outputs or output enables.

Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are

not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause

incorrect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is shown in the figure below.

Test- Logic

Reset

Run-Test/

Idle

Select-

DR-Scan

Capture-DR

Shift-DR

Exit1 -DR

Pause-DR

Exit2-DR

Select-

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-DR

Update-IR

11

0

0

0

1

1

0

0

1

1

0

1

0

1

0

0

1

1

1

0

0

11

0

1

0

1

1

0

00

0