DA14680 datasheet(21/440 Pages) RENESAS

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Datasheet

Revision 3.1

14-Jan-2022

CFR0011-120-00-FM Rev 5

21 of 439

DA14680

Bluetooth Low Energy 4.2 SoC with FLASH

FINAL

Unit. Following this, the CPU will start executing code

from address 0x0. If the system is just powered-up,

then ROM resides at 0x0 hence the bootROM

sequence will be triggered. If the system was just

waken-up, then address 0x0 is remapped to either the

Data-RAM or one of the Non-Volatile resources of the

chip hence code is directly executed from there.

3.4.1 Power/Wakeup FSM

The hardware FSM is responsible for starting the main

LDOs of the system and power the main rails used for

supplying the digital and analog resources of the chip.

The flow chart of this state machine is presented in Fig-

ure 3. System clock after Power On Reset is released,

is the 32 kHz coming from an on-chip RC oscillator

(RC32K). The FSM will initially compare the voltages

between pins VBUS and VBAT. This embedded PMU

feature provides a digital signal for deciding which LDO

to start so that Vsys is powered up. Please refer to Fig-

ure 6 for an overview of the LDOs.

When VBUS is present (the system is connected to the

USB for recharging or software upgrading), the PMU

powers the whole system from VBUS instead of VBAT.

Therefore a dedicated LDO_USB will be started. The

LDO_USB has its own reference and will switch to the

Bandgap reference voltage as soon as this has settled.

When no VBUS is detected (no USB connection), the

LDO_VBAT will be turned on, followed by the Bandgap.

The LDO_VBAT also has its own reference for starting

up and will automatically switch to the Bandgap refer-

ence.

The next step is to start the LDO_IO2 and LDO_IO,

which provides power to the external rails, mostly tar-

geting QSPI FLASH if available. Then the LDO_CORE

is enabled to supply the VDD voltage (1.2 V) for the

digital core to start operating. From that point onwards

and provided that the LDOs are settled, the digital sys-

tem is up and running.

Next, both 16 MHz oscillators are started. The system

clock switches to the 16 MHz RC clock to start OTP

mirroring or any other initialisation procedure that has

to do with an QSPI FLASH.

Then the CPU can take over and either start executing

code from RAM or ROM. In the case of executing code

from RAM, it can switch on the SIMO DC-DC con-

verter, disable the LDOs to lower the power consump-

tion of the digital part and operate the radio. For a

detailed overview of the PMU, please refer to Figure 8

and for a representation of the timing of the power up/

wake up process refer to Figure 17.

The latency of the hardware FSM is not always the

same. It is depending on power up or wake up and

more specific, in the case of wake up, it depends on

the time the system has been sleeping before.

When powered up the default clock is the RC32 which

is close to 32 kHz. The time required for the completion

of the HW FSM is 16 clock cycles i.e. 0.5 ms. If the sys-

tem wakes up, then the sleep clock is used: either the

XTAL32K (32 kHz) or the RCX (11.7 kHz). Depending

on the amount of time slept, there might be some

energy in the LDOs left or not, hence the settling time

might be less than expected. This process might take

11 to 16 clock cycles i.e. minimum 0.35 ms, maximum

1.6 ms.

3.4.2 Goto Sleep FSM

After the sleep command has been issued (WFI), the

system will switch to operating on RC16M and the HW

FSM described in the flow chart of will take over:

Figure 3: Power/Wakeup FSM flow diagram

Start

VBUS > VBAT ?

Power On VSYS

Turn on LDO_VBAT

Power On VEXT

Turn on LDO_IO2

Power On VCORE

Turn on LDO_CORE

Switch to RC16

clock

End

Default clock is

RC32 or Sleep

Clock

Yes

Power On VSYS

Turn on LDO_USB

Power On VFLASH

Turn on LDO_IO

System clock is

RC16M

Untrimmed if power

Trimmed if Wake up

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