COMMERCIALTEMPERATURERANGE

IDTCV146

PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR

3

PIN DESCRIPTION

Pin Number

Name

Type

Description

1

PCI0

OUT

PCI clock

2

PCI1

OUT

PCI clock

3VDD_PCI

PWR

3.3V

4VSS_PCI

GND

GND

5

PCI2

OUT

PCI clock

6

PCI3

OUT

PCI clock

7

PCI4

OUT

PCI clock

8

PCI5

OUT

PCI clock

9VSS_PCI

GND

GND

10

VDD_PCI

PWR

3.3V

11

TEST_SEL/PCIF0

I/O

Test Select (sampled at VTT_PWRGD# assertion), see TEST_SEL table. PCI clock afterward, free

running.

12

ITP_EN/PCIF1

I/O

Pin38, 39, CPU_ITP/SRC6 select (sampled on VTT_PWRGD# assertion), HIGH = CPU_2PCI

clock. PCI clock afterward, running.

13

VDD48

PWR

3.3V

14

USB48 /FS_B

I/O

48MHz clock/ FS_B input

15

VSS48

GND

GND

16

DOT96T

OUT

96MHz 0.7V current mode differential clock output

17

DOT96C

OUT

96MHz 0.7V current mode differential clock output

18

VTT_PWRGD#/PD

I N

3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C, TEST_SEL and

ITP_EN inputs, VTT_PWRGD# is low assertion/ After VTT_PWRGD# assertion, becomes a real-time

input for asserting power down (active HIGH).

19

SRCT0

OUT

Differential Serial reference clock

20

SRCC0

OUT

Differential Serial reference clock

21

SRCT1

OUT

Differential Serial reference clock

22

SRCC1

OUT

Differential Serial reference clock

23

VDD_SRC

PWR

3.3V

24

VSS_SRC

GND

GND

25

SRCT2

OUT

Differential Serial reference clock

26

SRCC2

OUT

Differential Serial reference clock

27

SRCT_SATA

OUT

SATA clock

28

SRCC_SATA

OUT

SATA clock

29

VDD_SRC

PWR

3.3V

30

SRCC3

OUT

Differential Serial reference clock

31

SRCT3

OUT

Differential Serial reference clock

32

SRCC4

OUT

Differential Serial reference clock

33

SRCT4

OUT

Differential Serial reference clock

34

VSS_SRC

GND

GND

35

SRCC5

OUT

Differential Serial reference clock

36

SRCT5

OUT

Differential Serial reference clock

37

VDD_SRC

PWR

3.3V

38

CPUC2_ITP/ SRCC6

OUT

Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCC6.

39

CPUT2_ITP/ SRCT6

OUT

Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCT6.

40

VDD_A

PWR

3.3V

41

VSS_A

GND

GND

42

IREF

OUT

Referencecurrentfordifferentialoutputbuffer