HS-80C86RH datasheet(21/30 Pages) RENESAS

21 / 30 page

HS-80C86RH

FN3035 Rev 0.00

Page 21 of 30

August 2000

Halt

When a software “HALT” instruction is executed the processor

indicates that it is entering the “HALT” state in one of two ways

depending upon which mode is strapped. In minimum mode,

the processor issues one ALE with no qualifying bus control

signals. In maximum mode the processor issues appropriate

HALT status on S2, S1, S0 and the 82C88 bus controller

issues one ALE. The HS-80C86RH will not leave the “HALT”

state when a local bus “hold” is entered while in “HALT”. In this

case, the processor reissues the HALT indicator at the end of

the local bus hold. An NMl or interrupt request (when interrupts

enabled) or RESET will force the HS-80C86RH out of the

“HALT” state.

Read/Modify/Write (Semaphore)

Operations Via Lock

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the execution

of an instruction. This gives the processor the capability of

performing read/modify/write operations on memory (via the

Exchange Register With Memory instruction, for example)

without another system bus master receiving intervening

memory cycles. This is useful in multiprocessor system

configurations to accomplish “test and set lock” operations.

The LOCK signal is activated (forced LOW) in the clock cycle

following decoding of the software “LOCK” prefix instruction. It

is deactivated at the end of the last bus cycle of the instruction

following the “LOCK” prefix instruction. While LOCK is active a

request on a RQ/GT pin will be recorded and then honored at

the end of the LOCK.

External Synchronization Via TEST

As an alternative to interrupts, the HS-80C86RH provides a

single software-testable input pin (TEST). This input is utilized

by executing a WAIT instruction. The single WAIT instruction is

repeatedly executed until the TEST input goes active (LOW).

The execution of WAIT does not consume bus cycles once the

queue is full.

If a local bus request occurs during WAIT execution, the

HS-80C86RH three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold circuits. If

interrupts are enabled, the HS-80C86RH will recognize

interrupts and process them when it regains control of the bus.

The WAIT instruction is then refetched, and reexecuted.

Basic System Timing

Typical system configurations for the processor operating in

minimum mode and in maximum mode are shown in Figures

14A and 14B, respectively. In minimum mode, the MN/MX pin

is strapped to VDD and the processor emits bus control signals

(e.g. RD, WR, etc.) directly. In maximum mode, the MN/MX pin

is strapped to GND and the processor emits coded status

information which the 82C88 bus controller used to generate

Multibus™ compatible bus control signals. Figure 11 shows the

signal timing relationships.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the Address

Latch Enable (ALE) signal. The trailing (low-going) edge of this

signal is used to latch the address information, which is valid

on the address/data bus (AD0-AD15) at this time, into the

82C82 latches. The BHE and A0 signals address the low, high

or both bytes. From T1 to T4 the M/IO signal indicates a

memory or I/O operation. At T2, the address is removed from

the address/data bus and the bus is held at the last valid logic

state by internal bus hold devices. The read control signal is

also asserted at T2. The read (RD) signal causes the

addressed device to enable its data bus drivers to the local

bus. Some time later, valid data will be available on the bus

and the addressed device will drive the READY line HIGH.

When the processor returns the read signal to a HIGH level,

the addressed device will three-state its bus drivers. If a

transceiver is required to buffer the HS-80C86RH local bus,

signals DT/R and DEN are provided by the HS-80C86RH.

A write cycle also begins with the assertion of ALE and the

emission of the address. The M/IO signal is again asserted to

ALE

LOCK

INTA

AD0-

FLOAT

TYPE

AD15

T4 TI

VECTOR

FIGURE 13. INTERRUPT ACKNOWLEDGE SEQUENCE

FLAGSH

FLAGSL

ACCUMULATOR

BASE

COUNT

DATA

STACK POINTER

BASE POINTER

SOURCE INDEX

DESTINATION INDEX

INSTRUCTION POINTER

STATUS FLAGS

CODE SEGMENT

DATA SEGMENT

STACK SEGMENT

EXTRA SEGMENT

TABLE 4. HS-80C86RH REGISTER MODEL

Multibus™ is a trademark of Intel Corporation.

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