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ICS8536-01 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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ICS8536-01 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 22 page ![]() Low Skew, 1-to-6, Crystal/ LVCMOS/ Differential-to-3.3V, 2.5V LVPECL Fanout Buffer ICS8536-01 DATA SHEET ICS8536-01 REVISION B AUGUST 17, 2012 1 GENERAL DESCRIPTION The ICS8536-01 is a low skew, high performance 1-to-6 Selectable Crystal, Single-Ended, or Differential Input-to- 3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-01 has selectable crystal, single ended or differential clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVPECL levels. The CLK1, nCLK1 pair can accept most standard differential input levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8536-01 ideal for those applications demanding well defined performance and repeatability. FEATURES • Six 3.3V, 2.5V LVPECL outputs • Selectable crystal oscillator, differential CLK1, nCLK1 pair or LVCMOS/LVTTL clock input • CLK1, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Crystal frequency range: 12MHz - 40MHz • Output skew: 55ps (maximum) CLK1, nCLK1 @ 3.3V • Part-to-part skew: 450ps (maximum) • Additive phase jitter, RMS: 0.19ps (typical) • Full 3.3V or 2.5V supply mode • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) packages PIN ASSIGNMENT 00 01 1X OSC D LE Q Q0 nQ0 Q5 nQ5 6 LVPECL Outputs Pullup Pullup Pulldown Pulldown Pulldown Pulldown CLK_EN CLK_SEL0 CLK_SEL1 XTAL_IN XTAL_OUT CLK0 CLK1 nCLK1 ICS8536-01 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BLOCK DIAGRAM nQ2 Q2 VCC nQ1 Q1 VEE nQ0 Q0 CLK_SEL0 XTAL_IN XTAL_OUT CLK_EN Q3 nQ3 VCC Q4 nQ4 VCC Q5 nQ5 CLK_SEL1 nCLK1 CLK1 CLK0 |
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