ICSSSTUAF32865A

2

8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

2

8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

13

ICSSSTUAF32865A

7097/1

1

Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)

Simulation Load Circuit

Voltage and Current Waveforms Inputs Active and Inactive

Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

Production-Test Load Circuit

Voltage Waveforms - Propagation Delay Times

Voltage Waveforms - Propagation Delay Times

NOTES:

1. CL includes probe and jig capacitance.

2. IDD tested with clock and data inputs held at VDD or GND, and

Io = 0mA

3. All input pulses are supplied by generators having the following

characteristics: PRR

≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns

±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per

measurement.

5. VTT = VREF = VDD/2

6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.

VIH = VDD for LVCMOS input.

7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.

VIL = GND for LVCMOS input.

8. VID = 600mV.

9. tPLH and tPHL are the same as tPDM.

CL =30 pF

RL =1K

DUT

Out

RL= 100

CLK Inputs

TL =50

TL =350ps, 50

Test Point

CLK

CLK

VDD

RL =1K

Test Point

Test Point

VDD

0V

VDD/2

LVCMOS

RESET

Input

IDD

VDD/2

tINACT

tACT

10%

90%

VICR

VID

VICR

Input

tW

VREF

VIH

VIL

VREF

Input

VICR

VID

tSU

tH

CLK

CLK

ZO =50

Test

Point

RL =50

DUT

Out

CLK Inputs

CLK

VDD/2

CLK

ZO =50

ZO =50

Test

Point

Test

Point

CLK

VICR

VID

tPLH

tPHL

Output

VOH

VOL

VICR

VTT

VTT

CLK

VOH

VOL

VIH

VIL

tRPHL

VDD/2

VTT

LVCMOS

RESET

Input

Output