13

1186G—04/16/07

ICSSSTUB32871A

Notes: 1. CL incluces probe and jig capacitance.

2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.

3. All input pulses are supplied by generators having the following chareacteristics: PRR

≤10 MHz,

Zo=50

Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. VREF = VDD/2

6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.

7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.

8. VID = 600 mV

9. tPLH and tPHL are the same as tPDM.

RL = 1000Ω

CL = 30 pF

(see Note 1)

LOAD CIRCUIT

tw

VICR

VICR

Inpu t

VIH

VIL

VOLTAGE WAVEFORMS – PULSE DURATION

VREF

VREF

Inpu t

tsu

th

VID

VICR

VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES

VICR

VID

VICR

Output

VOL

VOH

VTT

VTT

tPHL

tPLH

VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES

tRPHL

VOL

VOH

VIL

VIH

Output

VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES

VDD/2

VTT

tact

tinact

LVCMOS

Input

RST

VOLTAGE AND CURRENT WAVEFORMS

IDD

(see

Note 2)

90%

10%

INPUTS ACTIVE AND INACTIVE TIMES

0 V

VDD

Test Point

VDD/2

VDD/2

VCMOS

Inp ut

RST

TL=350ps, 50

Ω

DUT

CK

Out

TL=50

Ω

CK Inputs

VID

CK

CK

CK

CK

RL = 100Ω

CK

Test Point

Test Point

RL = 1000Ω

VDD

Figure 6

Parameter Measurement Information (V

= 1.8V 0.1V)

—

DD

±