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NB6L14M Datasheet(PDF) 5 Page - ON Semiconductor |
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NB6L14M Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 11 page ![]() NB6L14M http://onsemi.com 5 Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C (Note 9) Symbol Characteristic Min Typ Max Unit VOUTPP Output Voltage Amplitude (@ VINPPmin) (Note 10) fin ≤ 2.5 GHz 2.5 GHz ≤ fin ≤ 3.0 GHz 180 100 280 200 mV tPD Propagation Delay IN to Q 230 350 480 ps tS Set−Up Time (Note 11) EN to IN, IN 300 ps tH Hold Time (Note 11) EN to IN, IN 300 ps tSKEW Within−Device Skew (Note 12) Device−to−Device Skew (Note 13) 5.0 20 80 ps tDC Output Clock Duty Cycle fin ≤ 3.0 GHz (Referenced Duty Cycle = 50%) 40 50 60 % tJITTER RMS Random Jitter (Note 14) fIN ≤ 3.0 GHz Peak−to−Peak Data Dependent Jitter (Note 15) fIN ≤ 3.0 GHz 0.2 20 0.5 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) 100 2800 mV tr,tf Output Rise/Fall Times (20%−80%) 70 90 150 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (minimum) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20%−80%). 10.Input and output voltage swing is a single−ended measurement operating in differential mode. 11. Set−up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set−up and hold times do not apply. 12.Within device skew is measured between two different outputs under identical power supply, temperature and input conditions. 13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 14.Additive RMS jitter with 50% duty cycle clock signal. 15.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 23−1 and K28.5 at 2.5 Gb/s. |
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