Nexperia

74LVC86A

Quad 2-input EXCLUSIVE-OR gate

4. Functional diagram

mna787

1A

1B

1Y

2

1

3

2A

2B

2Y

5

4

6

3A

3B

3Y

10

9

8

4A

4B

4Y

13

12

11

Fig. 1. Logic symbol

mna786

3

=1

=1

=1

=1

2

1

6

5

4

8

10

9

11

13

12

Fig. 2. IEC logic symbol

mna788

Y

A

B

Fig. 3. Logic diagram for one gate

5. Pinning information

5.1. Pinning

74LVC86A

aaa-033852

1

2

3

4

5

6

7

8

10

9

12

11

14

13

VCC

4B

4A

4Y

3B

3A

1A

1B

1Y

2A

2B

2Y

GND

3Y

Fig. 4. Pin configuration

SOT108-1 (SO14)

74LVC86A

aaa-033853

1

2

3

4

5

6

7

8

10

9

12

11

14

13

VCC

4B

4A

4Y

3B

3A

1A

1B

1Y

2A

2B

2Y

GND

3Y

Fig. 5. Pin configuration

SOT402-1 (TSSOP14)

aaa-033854

74LVC86A

Transparent top view

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

4B

4A

4Y

3B

1B

1Y

2A

2B

2Y

3A

GND(1)

(1) This is not a ground pin. There

is no electrical or mechanical

requirement to solder the pad. In

case soldered, the solder land

should remain floating or connected

to GND.

Fig. 6. Pin configuration

SOT762-1 (DHVQFN14)

74LVC86A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 19 August 2021

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