ADT7473 datasheet(21/76 Pages) AD

21 / 76 page

ADT7473

Rev. A | Page 21 of 76

orms round-robin

tive of the ADT7467. As

esu

e ADT7473 is the same as

even though the

sync

are stored in Interrupt Status

f limits, the corresponding status register

bit is set to 1.

he serial bus. In Bit 7 (OOL) of

eans an out-of-limit

ister 2. This means

is set. Alternatively, Pin 5 or Pin 9 can be configured as an

As mentioned previously, the ADC perf

conversions. The total monitoring cycle time for averaged voltage

and temperature monitoring is 146 ms. The total monitoring cycle

time for voltage and temperature monitoring with averaging

disa led is 19 ms. The ADT7473 is a deriva

a r

lt, the total conversion time in th

the otal conversion time of the ADT7467,

AD 7473 has fewer monitored channels.

Fan TACH measurements are made in parallel and are not

hronized with the analog measurements in any way.

INTERRUPT STATUS REGISTERS

The results of limit comparisons

for each channel reflects the status of the last measurement an

limit comparison on that channel. If a measurement is within

limits, the corresponding status register bit is cleared to 0. If the

measurement is out o

e state of the various measurement channels can be polled by

reading the status registers over t

Interrupt Status Register 1 (Reg. 0x41), a 1 m

event has been flagged in Interrupt Status Reg

the user needs only to read Interrupt Status

SMBALERT output. This automatically notifies the system

supervisor of an out-of-limit condition. Reading the status registe

clears the appropriate status bit as long as the error condition

caused the interrupt has cleared. Status register bits (excep

that

t OVT)

dicating an out-of-limit

the

urces to be masked from causing an SMBALERT

are sticky. Whenever a status bit is set, in

condition, it remains set even if the event that caused it has go

away (until read). The only way to clear the status bit is to read

status register after the event has gone away. Interrupt mask

registers (Register 0x74 and Register 0x75) allow individual

interrupt so

it,

Bit 7 (OOL) = 1, denot

errupt Status Register 2 is

been

or low limit has

ed.

on D1+/D1– inputs.

w the

minimum speed. Alternatively, it indicates the THERM

However, if one of these masked interrupt sources goes out of lim

its associated status bit is set in the interrupt status registers. OVT

clears automatically.

Interrupt Status Register 1 (0x41)

es a bit in Int

set and Interrupt Status Register 2 should be read.

Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has

been exceeded.

Bit 5 (LT) = 1, local temperature high or low limit has

exceeded.

Bit 4 (R1T) = 1, Remote 1 temperature high

been exceeded.

Bit 2 (V ) = 1, V

high or low limit has been exceede

Bit 1 (VCCP) = 1, VCCP high or low limit has been exceed

Interrupt Status Register 2 (0x42)

Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.

Bit 6 (D1) = 1, indicates an open or short

Bit 5 (F4P) = 1, indicates Fan 4 has dropped belo

limit

has been exceeded, if the THERM function is used.

low the

n 2 has dropped below the

s a THERM

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped be

minimum speed.

Bit 3 (FAN2) = 1, indicates Fa

minimum speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below the

minimum speed.

Bit 1 (OVT) = 1, indicate

overtemperature limit has

been exceeded.

SMBALER Interrupt Behavior

The ADT7473 can be polled for status, or an SMBALERT

itions. It is

interrupt can be generated for out-of-limit cond

important to note how the SMBALERT output and st

behave when writing interrupt handler software.

atus bits

STICKY

HIGH LIMIT

ATUS BIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

Figure 26. SMBALERT and Status Bit Behavior

Figure 26 shows how the SMBALERT output and sticky stat

bits behave. Once a limit is exceeded, the corresponding status

bit is set to 1. The interrupt status bit remains set until t

condition sub

status bits are r

he error

sides and the interrupt status register is read. The

eferred to as sticky because they remain set until

annot

read by software. This ensures that an out-of-limit event c

be missed if software is polling the device periodically. Note

that the SMBALERT output remains low for the entire duration

that a reading is out of limit and until the interrupt status

handles the interrupt.

Note: THERM overtemperature events are not sticky, resetting

immediately after the overtemperature condition ceases. This

also applies to SMBALERT if associated with an OVT event.

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