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AD5384BBC-5 Datasheet(PDF) 10 Page - Analog Devices

Part # AD5384BBC-5
Description  40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5384BBC-5 Datasheet(HTML) 10 Page - Analog Devices

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AD5384
Rev. A | Page 10 of 36
TIMING CHARACTERISTICS
SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 7.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5 4
13
ns min
24th SCLK falling edge to SYNC falling edge
t64
33
ns min
Minimum SYNC low time
t7
10
ns min
Minimum SYNC high time
t7A
50
ns min
Minimum SYNC high time in readback mode
t8
5
ns min
Data setup time
t9
4.5
ns min
Data hold time
t104
30
ns max
24th SCLK falling edge to BUSY falling edge
t11
670
ns max
BUSY pulse width low (single channel update)
t124
20
ns min
24th SCLK falling edge to LDAC falling edge
t13
20
ns min
LDAC pulse width low
t14
100
ns max
BUSY rising edge to DAC output response time
t15
0
ns min
BUSY rising edge to LDAC falling edge
t16
100
ns min
LDAC falling edge to DAC output response time
t17
8
µs typ
DAC output settling time boost mode off
t18
20
ns min
CLR pulse width low
t19
12
µs max
CLR pulse activation time
t20 5
20
ns max
SCLK rising edge to SDO valid
t215
5
ns min
SCLK falling edge to SYNC rising edge
t225
8
ns min
SYNC rising edge to SCLK rising edge
t23
20
ns min
SYNC rising edge to LDAC falling edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD), and are timed from a voltage level of 1.2 V.
3 See
, F
,
and
.
Figure 2 igure 3 Figure 5,
Figure 6
4 Standalone mode only.
5 Daisy-chain mode only.
CL
50pF
TO OUTPUT PIN
VOH (MIN) OR
VOL (MAX)
200
µA
200
µA
IOL
IOH
Figure 2. Load Circuit for Digital Output Timing



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