AD15252

Rev. 0 | Page 12 of 20

A single channel can be powered down for moderate power

savings. The powered-down channel shuts down internal

circuits, but both the reference buffers and shared reference

remain powered. Because the buffer and voltage reference

remain powered, the wake-up time is reduced to several clock

cycles.

The data format can be selected for either offset binary or twos

complement. This is discussed later in the Data Format section.

TIMING

The AD15252 provides latched data outputs with a pipeline

delay of seven clock cycles. Data outputs are available one

Refer to

When using only one channel of the AD15252, the clock for the

disabled channel should also be disabled, or distortion occurs in

the channel in use.

Figure 20 for a detailed timing diagram.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD15252. These transients can detract from the converter’s

dynamic performance.

DIGITAL OUTPUTS

The AD15252 output drivers can be configured to interface

with 2.5 V or 3.3 V logic families by matching DRVDD to the

digital supply of the interfaced logic. The output drivers are

sized to provide sufficient output current to drive a wide variety

of logic families. However, large drive currents tend to cause

current glitches on the supplies, which can affect converter

performance. Applications requiring the ADC to drive large

capacitive loads or large fan-outs can require external buffers or

latches.

The lowest typical conversion rate of the AD15252 is 1 MSPS.

At clock rates below 1 MSPS, dynamic performance can degrade.

DATA FORMAT

The AD15252 data output format can be configured for either

twos complement or offset binary. This is controlled by the data

format select pin (DFS). Connecting DFS to AGND produces

offset binary output data. Conversely, connecting DFS to AVDD

formats the output data as twos complement.

ANALOG INPUT

ADC A

ANALOG INPUT

ADC B

CLK_A = CLK_B =

MUX_SELECT

D0_A

–D11_A

Figure 20. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT