Nexperia

74LVC1G57

Low-power configurable multiple function gate

7.1. Logic configurations

Table 5. Function selection table

Logic function

Figure

2-input AND

see Fig. 5

2-input AND with both inputs inverted

see Fig. 8

2-input NAND with inverted input

see Fig. 6 and Fig. 7

2-input OR with inverted input

see Fig. 6 and Fig. 7

2-input NOR

see Fig. 8

2-input NOR with both inputs inverted

see Fig. 5

2-input XNOR

see Fig. 9

Inverter

see Fig. 10

Buffer

see Fig. 11

001aab584

B

B

6

Y

C

1

5

2

4

3

Y

Y

C

B

C

VCC

Fig. 5. 2-input AND gate or

2-input NOR gate with both inputs inverted

001aab585

B

B

6

Y

C

1

5

2

4

3

Y

Y

C

B

C

VCC

Fig. 6. 2-input NAND gate with input B inverted or

2-input OR gate with inverted C input

001aab586

A

A

6

Y

C

1

5

2

4

3

Y

Y

C

A

C

VCC

Fig. 7. 2-input NAND gate with input C inverted or

2-input OR gate with inverted A input

001aab587

A

6

C

1

5

2

4

3

Y

VCC

A

Y

C

Y

A

C

Fig. 8. 2-input NOR gate or

2-input AND gate with both inputs inverted

001aab588

B

6

C

1

5

2

4

3

Y

VCC

Y

B

C

Fig. 9. 2-input XNOR gate

001aab589

A

A

6

Y

1

5

2

4

3

Y

VCC

Fig. 10. Inverter

001aab590

B

B

6

Y

1

5

2

4

3

Y

VCC

Fig. 11. Buffer

74LVC1G57

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2022. All rights reserved

Product data sheet

Rev. 10 — 1 February 2022

4 / 18