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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

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│ 32

Figure 41:

Output Bit Rate for Each Transmission Mode

Serial Word Width

Output Bit Rate

8-bit

640 MHz @ 80 MHz MCLK

12-bit

720 MHz @ 60 MHz MCLK

The ADC resolution (End of Range, register 0x0A) should be adjusted to match with the achieved line

rate and serial word width.

If using a different MCLK, please check which PLL Division to use, as reference in the below section

7.8.

7.8

Internal Clock

The sensor presents a PLL that will generate a faster clock according to the input main clock

frequency (MCLK) and transmission mode.

Figure 42:

Main Clock According to the Transmission Mode

Transmission Mode

Maximum MCLK

[MHz]

PLL Clock

Frequency

[MHz]

PLL Clock

Period [ps]

DDR Clock

[MHz]

8-bit

640

1.56

320

12-bit

720

1.39

360

The PLL also includes a division block to promote the possibility of a lower frequency clock.

Figure 43:

Internal Clock Generation

Bit [2:0]

Main Clock

0, 2, 4, 8, 16

PLL Clock

4LS5K Datasheet(PDF) 33 Page - ams AG

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