TSB41AB3IPFP datasheet(15/52 Pages) TI

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TSB41AB3

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

tsu

D, CTL, LREQ

SYSCLK

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

D, CTL, LREQ

SYSCLK

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

APPLICATION INFORMATION

internal register configuration

There are 16 accessible internal registers in the TSB41AB3. The configuration of the registers at addresses 0h

through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the

paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected.

The selected page is set in base register 7h.

The configuration of the base registers is shown in Table 1, and corresponding field descriptions given in

Table 2. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables)

is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 1. Base Register Configuration

Address

BIT POSITION

Address

0000

Physical ID

CPS

0001

RHB

IBR

Gap_Count

0010

Extended (111b)

Rsvd

Num_Ports (0011b)

0011

PHY_Speed (010b)

Rsvd

Delay (0000b)

0100

LCtrl

Jitter (000b)

Pwr_Class

0101

RPIE

ISBR

CTOI

CPSI

STOI

PEI

EAA

EMC

0110

Reserved

0111

Page_Select

Rsvd

Port_Select

TSB41AB3IPFP Datasheet(PDF) 15 Page - Texas Instruments

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