AD73411 datasheet(21/36 Pages) AD

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AD73411

–21–

In Cascade Mode, each device must know the number of devices

in the cascade because the Data and Mixed modes use a method

of counting input frame sync pulses to decide when they should

update the DAC register from the serial input register. Control

by the DSP during the programming phase. The default condi-

tion is that the ﬁeld contains 000b, which is equivalent to a

single device in cascade (see Table XVI). For cascade operation,

however this ﬁeld must contain a binary value that is one less

than the number of devices in the cascade.

Table XVI. Device Count Settings

DC2

DC1

DC0

Cascade Length

000

001

010

011

100

101

110

111

FUNCTIONAL DESCRIPTION—DSP

The AD73411 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The AD73411 assembly language uses an algebraic

syntax for ease of coding and readability. A comprehensive set

of development tools supports program development.

EXTERNAL

ADDRESS

BUS

HOST MODE

SERIAL PORTS

SPORT 0

SHIFTER

MAC

ALU

ARITHMETIC UNITS

MEMORY

PROGRAMMABLE

I/O

AND

FLAGS

BYTE DMA

CONTROLLER

TIMER

ADSP-2100 BASE

ARCHITECTURE

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2

DATA

ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

INTERNAL

DMA

PORT

DAG 1

16K DM

(OPTIONAL

8K)

16K PM

(OPTIONAL

8K)

EXTERNAL

DATA

BUS

FULL MEMORY

MODE

EXTERNAL

DATA

BUS

SPORT 1

SERIAL PORT

SPORT 2

REF

ADC1

DAC1

ANALOG FRONT END

SECTION

Figure 12. Functional Block Diagram

Figure 12 is an overall block diagram of the AD73411. The

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division primi-

tives are also supported. The MAC performs single-cycle multiply,

multiply/add and multiply/subtract operations with 40 bits of

accumulation. The shifter performs logical and arithmetic shifts,

normalization, denormalization and derive exponent operations.

The shifter can be used to efﬁciently implement numeric

format control including multiword and block floating-point

representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efﬁcient delivery of operands to these com-

putational units. The sequencer supports conditional jumps,

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the AD73411 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modiﬁed by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

Efﬁcient data transfer is achieved with the use of ﬁve internal

buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

Program memory can store both instructions and data, permitting

the AD73411 to fetch two operands in a single cycle, one from

program memory and one from data memory. The AD73411

can fetch an operand from program memory and the next in-

struction in the same cycle.

In lieu of the address and data bus for external memory connec-

tion, the AD73411 may be conﬁgured for 16-bit Internal DMA

port (IDMA port) connection to external systems. The IDMA

port is made up of 16 data/address pins and ﬁve control pins.

The IDMA port provides transparent, direct access to the DSPs

on-chip program and data RAM.

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

external buses with bus request/grant signals (

BR, BGH, and

BG). One execution mode (Go Mode) allows the AD73411 to

continue running from on-chip memory. Normal execution

mode requires the processor to halt while buses are granted.

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