Nexperia

74HC03; 74HCT03

Quad 2-input NAND gate; open-drain output

10.1. Waveforms and test circuit

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nA, nB input

nY output

VI

VCC

VOL

10 %

90 %

GND

VM

VM

VX

tPLZ

tPZL

tTHL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 6. Input to output propagation delays

Table 8. Measurement points

Input

Output

Type

VM

VM

VX

74HC03

0.5VCC

0.5VCC

0.1VCC

74HCT03

1.3 V

1.3 V

0.1VCC

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig. 7. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPZL, tPLZ

74HC03

VCC

6 ns

15 pF, 50 pF

1 kΩ

VCC

74HCT03

3.0 V

6 ns

15 pF, 50 pF

1 kΩ

VCC

74HC_HCT03

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 10 August 2021

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