FWIXEEAD0SE001 datasheet(44/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

A15

A12

FIFOSEL1

FIFOSEL0

I, ID, ST

FIFO Select <1:0>.

These pins are read at startup or reset. Their value at

that time is used to set the default state of Register bits

18.15:14 for all ports. These register bits can be read

and overwritten after startup/reset.

These pins are shared with RMII-RxER<5:4>. An

external pull-up resistor (see applications section for

value) can be used to set FIFO Select<1:0> to active

while RxER<5:4> are three-stated during hardware

reset. If no pull-up is used, the default FIFO select

state is set via the internal pull-down resistors.

See Table 17, “Intel® LXT9785/LXT9785E Receive

FIFO Depth Considerations” on page 50.

PREASEL

I, ID, ST

Preamble Select.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 16.5 for

all ports. This register bit can be read and overwritten

after startup/reset.

This pin is shared with RMII-RxER2. An external pull-

up resistor (see applications section for value) can be

used to set Preamble Select to active while RxER2 is

three-stated during hardware reset. If no pull-up is

used, the default Preamble Select state is set via the

internal pull-down resistors.

Note: Preamble select has no effect in 100 Mbps

operation.

A17

LINKHOLD

LINKHOLD Default. This pin is read at startup or

reset. Its value at that time is used to set the default

state of Register bit 0.11 for all ports. This register bit

can be read and overwritten after startup / reset. When

High, the LXT9785/9785E powers down all ports.

This pin is shared with RMII-RxER6. An external pull-

up resistor (see applications section for value) can be

used to set LINKHOLD active while RxER6 is tri-stated

during H/W reset. If no pull-up is used, the default

LINKHOLD state is set inactive via the internal pull-

down resistor.

Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 4 of 4)

Pin/Ball

Designation

Symbol

Type1

Signal Description2

PQFP

PBGA

1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =

Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal

Pull-Down.

2. The IP/ID resistors are disabled during hardware power-down mode.

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