Nexperia

74LVC07A

Hex buffer with open-drain outputs

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal-Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

74LVC07A v.7

20200803

Product data sheet

-

74LVC07A v.6

Modifications:

• Section 1 and Section 2 updated.

• Table 4: Derating values for Ptot total power dissipation updated.

74LVC07A v.6

20181214

Product data sheet

-

74LVC07A v.5

Modifications:

• The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Table 5: Maximum output voltage (active mode) changed from VCC to 5.5 V

74LVC07A v.5

20111027

Product data sheet

-

74LVC07A v.4

Modifications:

• Table 7: values added for lower voltage ranges.

74LVC07A v.4

20110810

Product data sheet

-

74LVC07A v.3

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6 and Table 7: values added for lower voltage ranges.

74LVC07A v.3

20031111

Product specification

-

74LVC07A v.2

74LVC07A v.2

20030225

Product specification

-

74LVC07A v.1

74LVC07A v.1

20000307

Product specification

-

-

74LVC07A

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 7 — 3 August 2020

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