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TMPR4925 Datasheet(PDF) 119 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 119 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-9
7.3.6
Access Modes
The following four modes are available as controller access modes. These modes can be set
separately for each channel.
•
Normal mode
•
Page mode
•
External ACK mode
•
Ready mode
Depending on the combination of modes in each channel, either of two modes in which the
ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is
selected by the ACK*/Ready Mode bit (PCFG.ACKIN) of the Chip Configuration Register. The mode
selected is applied globally to all channels.
(1) ACK*/READY Dynamic mode (PCFG.ACKIN = 0)
This mode is selected in the initial state.
The ACK*/Ready signal automatically switches to either input or output according to the setting of
each channel. When in the Normal mode or the Page mode, the ACK*/Ready signal is an output
signal, and the internally generated ACK* signal is output. When in the External ACK* or Ready
mode, the ACK*/Ready signal becomes an input signal. The ACK*/Ready signal outputs High if
there is no access to the External Bus Controller. However, this signal may output Low during
access to SDRAM.
Please refer to the timing diagrams (Figure 7.5.23 and Figure 7.5.24) and be careful to avoid
conflicts when switching from output to input.
(2) ACK*/Ready Static mode (PCFG.ACKIN = 1)
The internally generated ACK* signal is not output when in either the Normal mode or Page mode.
Therefore, the ACK*/Ready signal will not become an output in any channel.
Access using Burst transfer by the internal bus (G-Bus) is supported when in a mode other than the
Ready mode. However, the Ready mode is not supported.
Table 7.3.7 Operation Mode
PM
RDY
EACK
Mode
ACK*/READY
Pin State
Access End
Timing State
G-Bus Burst
Access
0Normal
Output
Internally
Generated ACK*
√
0
1
External ACK*
Input
ACK* Input
√
0
1
READY
Input
Ready Input
0
Page
Output
Internally
Generated ACK*
√
ACK*/Ready
Dynamic Mode
!0
1
Reserved

0Normal
Hi-Z
Internally
Generated ACK*
√
0
1
External ACK*
Input
ACK* Input
√
0
1
READY
Input
Ready Input
0
Page
Hi-Z
Internally
Generated ACK*
√
ACK*/Ready
Static Mode
!0
1
Reserved




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