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TMPR4925 Datasheet(PDF) 122 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 122 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-12
7.3.7
Access Timing
7.3.7.1
SHWT Option
The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel
Control Register is a value other than “0”. This option inserts a Setup cycle and a Hold cycle
between the current signal and the next signal.
Setup cycle: CE* from ADDR, OE* from CE*, BWE* from CE*, SWE* from CE*
Hold cycle: ADDR from CE*, CE* from OE*, CE* from BWE*, CE* from SWE*
This option is used for I/O devices that are generally slow. All Setup cycles and Hold cycles
will be identical, so each cycle cannot be set individually.
The SHWT mode cannot be used by the Page mode. The SHWT mode can be used by all other
modes, but there is one restriction: the internal bus cannot use Burst access.
Figure 7.3.5 SWHT Disable (Normal Mode, Single Read/Write Cycle)
Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle)
SYSCLK
CE*/BE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Output)
EBCCRn.PWT:WT=0
EBCCRn.SHWT=0
SWE*/BWE*
SYSCLK
CE*/BE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Output)
EBCCRn.PWT:WT=0
EBCCRn.SHWT=1
SWE*/BWE*



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