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TMPR4925 Datasheet(PDF) 131 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 131 Page - Toshiba Semiconductor |
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131 / 590 page  Chapter 7 External Bus Controller 7-21 7.3.9.5 PCMCIA IOIS16* Signal The IOIS16* signal is not supported. This means that the size of IO accesses needs to be known ahead of time and are not dynamically sized. 7.3.9.6 PCMCIA Cycle Types Burst Cycles are not allowed on a PCMCIA enabled Channel. This is due to the fact that the EBUSC Controller does not toggle all signals between the individual accesses for burst accesses. The PCMCIA specification requires that all signals toggle per each access. In addition programming requirements for a channel supporting PCMCIA require SHWT mode. Burst accesses are not allowed with SHWT enabled. Table 7.3.8 Access Mapping (PCMCIA in 16-bit Channel and Little Endian Mode) Access Access Address ADDR[1:0] Port Size CARDnCSH*, CARDnCSL* DATA[15:8] DATA[7:0] Word(1/2) 00 16-bit LL R[15:8] R[7:0] Word{2/2} 00 10 16-bit LL R[31:24] R[23:16] Triple byte(1/2) 00 16-bit LH R[15:8] - Triple byte(2/2) 01 10 16-bit LL R[31:24] R[23:16] Triple byte(1/2) 00 16-bit LL R[15:8] R[7:0] Triple byte(2/2) 00 10 16-bit HL - R[23:16] Half-Word 10 10 16-bit LL R[15:8] R[7:0] Half-Word 00 00 16-bit LL R[15:8] R[7:0] Byte 11 10 16-bit LH R[7:0] - Byte 10 10 16-bit HL - R[7:0] Byte 01 00 16-bit LH R[7:0] - Byte 00 00 16-bit HL - R[7:0] Note: Word access and triple byte access yield 2 separate external cycles. Table 7.3.9 Access Mapping (PCMCIA in 8-bit Channel and Little Endian Mode) Access Access Address ADDR[1:0] Port Size CARDnCSH*, CARDnCSL* DATA[15:8] DATA[7:0] Word(1/4) 00 8-bit HL - R[7:0] Word{2/4} 01 8-bit HL - R[15:8] Word(3/4) 10 8-bit HL - R[23:16] Word{4/4} 00 11 8-bit HL - R[31:24] Triple byte(1/3) 01 8-bit HL - R[15:8] Triple byte(2/3) 10 8-bit HL - R[23:16] Triple byte(3/3) 01 11 8-bit HL - R[31:24] Triple byte(1/3) 00 8-bit HL - R[7:0] Triple byte(2/3) 01 8-bit HL - R[15:8] Triple byte(3/3) 00 10 8-bit HL - R[23:16] Half-Word(1/2) 10 8-bit HL - R[7:0] Half-Word(2/2) 10 11 8-bit HL - R[15:8] Half-Word(1/2) 00 8-bit HL - R[7:0] Half-Word(2/2) 00 01 8-bit HL - R[15:8] Byte 11 11 8-bit HL - R[7:0] Byte 10 10 8-bit HL - R[7:0] Byte 01 01 8-bit HL - R[7:0] Byte 00 00 8-bit HL - R[7:0] Note: Word access yields 4 separate external cycles. Triple byte access yields 4 separate external cycles. Half-word access yields 4 separate external cycles. |
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