TMPR4925 datasheet(134/590 Pages) TOSHIBA

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Chapter 7 External Bus Controller

7-24

7.4.1

External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1)

0x9010 (ch. 2), 0x9018 (ch. 3)

0x9020 (ch. 4), 0x9028 (ch. 5)

0x9030 (ch. 6), 0x9038 (ch. 7)

Channel 0 and 7 can be used as Boot memory. Therefore, the default is set by the Boot signal (see

“7.3.2 Global/Boot-up Options”). Channels 1 - 7 have the same register configuration as Channel 0, but

they have different defaults than Channel 0.

LDEA

EACK

Reserved

PCM

PCS

Reserved

BSZ

PWT

R/W

: Type

~A[5](ch0,7)/

0(ch1~6)

~A[5]/0

000

000(ch0-6)/001(ch7)

1(ch0,7)/

0(ch1~6)

A[13:12](ch0,7)/

00(ch1~6)

11(ch0,7)/00(ch1-6)

: Initial value

876

5432

RDY

SHWT

R/W

: Type

1111(ch0,7)/0000(ch1~6)

0010(ch0,7)/0000(ch1-6)

A[11]

(ch0,7)/

0(ch1-6)

0(ch0-6)/

1(ch7)

A[4:3]/00

A[8]/0

000(ch0-6)/111(ch7)

: Initial value

Only in the case of Channel 0 is fields with different defaults in the “Channel 0/Other channel” state.

D[ ] represents the corresponding Data[ ] signal value when the RESET* signal is deasserted. A[ ] represents

the corresponding ADDR[ ] signal value when the RESET* signal is deasserted.

Bits

Mnemonic

Field Name

Description

LDEA

Latch Data at

External ACK*

Latch Data at External ACK* (Initial value: ~A[5](ch0,7)/0(ch1~6), R/W)

Specifies the data latched timing in the external ACK* input mode.

0 : Data is latched for External ACK* Input mode Reads at OE* active.

1 : Data is latched for External ACK* Input mode Reads at ACK* active.

EACK

ACK* Input

Active

ACK* Input Active (Initial value: ~A[5]/0, R/W)

Enable ACK* Input mode.

0 : ACK* Input mode is disabled.

1 : ACK* Input mode is enabled.

29 : 27



Reserved

Note: These bits are always set to “0” (Initial value: 000, R/W).

Figure 7.4.1 External Bus Channel Control Register (1/3)

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