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TMPR4925 Datasheet(PDF) 240 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 240 Page - Toshiba Semiconductor |
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240 / 590 page  Chapter 9 SDRAM Controller 9-12 writes function normally in 16-bit mode. This is caused by two external accesses always being performed for each data access of 16 bits or less when the bus width is 16 bits. These two bus cycles do not output odd addresses in order to execute Burst transfer. Therefore, device IDs with an odd address and Device Protect bits cannot be accessed. 9.4 Registers Table 9.4.1 SDRAM Control Register Reference Offset Address Bit Width Register Symbol Register Name 9.4.1 0x8000 32 SDCCR0 SDRAM Channel Control Register 0 9.4.1 0x8004 32 SDCCR1 SDRAM Channel Control Register 1 9.4.1 0x8008 32 SDCCR2 SDRAM Channel Control Register 2 9.4.1 0x800C 32 SDCCR3 SDRAM Channel Control Register 3 9.4.2 0x8020 32 SDCTR SDRAM Timing Register 9.4.3 0x802C 32 SDCCMD SDRAM Command Register 9.4.4 0x8030 32 SFCMD SyncFlash Command Register |
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