TMPR4925 datasheet(277/590 Pages) TOSHIBA

277 / 590 page

Chapter 10 PCI Controller

10-15

Figure 10.3.8 Transition of the Power Management States

10.3.9

PDMAC (PCI DMA Controller)

The PCI DMA Controller (PDMAC) is a one-channel PCI Director Memory Access (DMA)

controller. Data can be transferred bidirectionally between the G-Bus and the PCI Bus.

10.3.9.1 DMA Transfer

The following DMA transfer procedure does not use the Chain DMA mode.

(1) Address Register and Count Register Setting

Sets values for the three following registers.

•

PDMAC G-Bus Address Register (PDMGA)

•

PDMAC PCI Bus Address Register (PDMPA)

•

PDMAC Count Register (PDMCTR)

(2) Chain Address Register Setting

Sets “0” to the PDMAC Chain Address Register (PDMCA).

(3) PDMAC Status Register (PDMSTATUS) Clearing

Clears any remaining status from a previous DMA transfer.

(4) PDMAC Control register (PDMCFG) Setting

Clears the Channel Reset bit (CHRST), and makes settings such as the data transfer direction

(XFRDIRC), and the burst mode (BRSTMD).

(5) DMA Transfer Initiation

Setting the Transfer Active bit (XFRACT) of the PDMAC Control Register initiates DMA

transfer.

Uninitialized

D0 Active

D3hot

D3cold

PCI RST*

(RESET*

VCC Cut-off

Software Reset

Power On Reset

(RESET*

Initialization by the

System Software

Change PMCSR

PowerState

TMPR4925 Datasheet(PDF) 277 Page - Toshiba Semiconductor