TMPR4925 datasheet(282/590 Pages) TOSHIBA

282 / 590 page

Chapter 10 PCI Controller

10-20

10.3.11 PCI Bus Arbiter

Configuration settings (ADDR[1] signal = “1”) during boot up selects whether to use the on-chip PCI

Bus arbiter (Internal PCI Bus Arbiter mode) or to use the External PCI Bus arbiter (External PCI Bus

Arbiter mode).

When in the Internal PCI Bus Abiter mode, setting the PCI Bus Arbiter Enable bit

(PBACFG.PBAEN) of the PCI Bus Arbiter Configuration Register starts operation.

The on-chip PCI Bus arbiter can arbitrate eight sets of PCI Bus usage requests from the Bus Master.

Five ports are used: one for the PCI Controller bus master and four for External Bus masters. The three

remaining ports are reserved for future expanded features.

10.3.11.1 Request Signal, Grant Signal

The four external Bus Masters are connected to the REQ[3:0] signal and the GNT[3:0]* signal.

Also, when in the External PCI Bus Arbiter mode (Satellite Mode), the REQ[0]* signal

becomes the PCI Bus Request Output signal and the GNT[0]* signal becomes the Bus Usage

Permission Input Signal. Furthermore, the REQ[1]* signal can be used as an interrupt output

signal to the external devices (see 14.3.7 for more information).

10.3.11.2 Priority Control

As illustrated below in Figure 10.3.9, a combination of two round-robin sequences is used as

the arbitration algorithm that determines the priority of Internal PCI Bus arbiter bus requests. The

round-robin with the lower priority (Level 2) consists of Masters W - Z, and the round-robin with

the high priority (Level 1), consists of Master A - D and Level 2 Masters. The PCI Bus Arbiter

Request Port Register (PBAREQPORT) specifies whether to allocate the PCI Controller and the

four External Bus Masters to Masters A-D or W - Z.

Figure 10.3.9 PCI Bus Arbitration Priority

The Bus Master priority is determined based on the Level 1 round-robin sequence. However,

when Level 2 is used inside Level 1, the Level 2 Bus Master priority is determined based on the

Level 2 round-robin sequence.

Level 2

(Priority: Low)

Level 1

(Prirority: High)

Master A

Level 2

Master Z

Master X

Master W

Master B

Master C

Master D

Master Y

TMPR4925 Datasheet(PDF) 282 Page - Toshiba Semiconductor