TMPR4925 datasheet(301/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-39

Bits

Mnemonic

Field Name

Description

G2PM2EN

Initiator Memory

Space 2 Enable

Initiator Memory Space 2 Enable (Initial value: Normal Mode: 0; PCI Boot Mode: 1,

R/W)

Controls PCI initiator access to Memory Space 2.

1: Memory Space 2 is valid.

0: Memory Space 2 is invalid.

4G2PIOEN

Initiator I/O Space

Enable

Initiator I/O Space Enable (Initial value: 0, R/W)

Controls PCI initiator access to the I/O Space..

1: I/O Space is valid.

0: I/O Space is invalid.

IRBER

Bus Error

Response Setting

During Initiator

Access

Initiator Access Bus Error Response (Initial value: 1, R/W)

Bus error responses on the G-Bus are controlled when the following phenomena

indicated by the PCI Status, Command Register (PICSTATUS) and the G2P Status

Detected Fatal Error (G2PSTATUS.MDFE)

Detected Parity Error (G2PSTATUS.MDPE)

Received Master Abort (PCISTATUS.RMA)

Received Target Abort (PCISTATUS.RTA)

Initiator Detected TRDY Time Out Error (G2PSTATUS.IDTTOE)

Initiator Detected Retry Time Out Error (G2PSTATUS.IDRTOE)

1: Responds with a Bus error on the G-Bus.

0: Does not respond with a Bus error on the G-Bus. (Normally terminates the

transaction on the G-Bus. Read data is invalid.)



Reserved



BSWAPI

Byte Swap for

Indirect, Config,

IACK, and

Special cycle

Byte Swap for Indirect, Config, IACK, and Special cycle

(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W)

Sets the byte swapping of Indirect, Config, IACK, and Special cycle.

0: Do not perform byte swapping.

1: Perform byte swapping.

Please use the default state in most situations. If this bit is changed to “0” when in the

Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-

bit) access will not change.

ASERR

Assert SERR

Assert SERR (Initial value: 0, R/W1C)

A write of 1 will assert SERR for 1 PCI clock. Always read 0.

Figure 10.4.13 G2P Configuration Register (2/2)

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