TMPR4925 datasheet(298/590 Pages) TOSHIBA

298 / 590 page

Chapter 10 PCI Controller

10-36

10.4.11 PCI Configuration 2 Register (PCICFG2)

0xD03C

The following fields correspond to the following registers:

Max. Latency field

→ Max_Lat Register of the PCI Configuration Space

Min. Grant field

→ Min_Gnt Register of the PCI Configuration Space

Interrupt Pin field

→ Interrupt Pin Register of the PCI Configuration Space

Interrupt Line field

→ Interrupt Line Register of the PCI Configuration Space.

A write to Register PCICDATA3 when PCICCFG.LCFG=1 will modify the contents of this register.

Otherwise this register is Read Only.

This register cannot be accessed when the PCI Controller is in the Satellite mode.

R/L

: Type

0x00

: Initial value

R/L

R/W

: Type

0x00

: Initial value

Bits

Mnemonic

Field Name

Description

31:24

Maximum

Latency

Max_Lat (Maximum Latency) (Initial value: 0x00, R/L)

00h: Does not use this register to determine PCI Bus priority.

01h-FFh: Specifies the time interval for requesting bus ownership.

In units of 250 ns, assuming the PCICLK is 33 MHz.

It is possible to change the maximum latency by software.

23:16

Minimum Grant

Min_Gnt (Minimum Grant) (Initial value: 0x00, R/L)

00h: Is not used to calculate the latency timer value.

01h-FFh: Sets the time required for Burst transfer.

In units of 250 ns, assuming the PCICLK is 33 MHz.

It is possible to change this valuesoftware.

15:8

Interrupt Pin

Interrupt Pin (Initial value: 0x00, R/L)

Valid values: 00 - 04h

00h: Do not use interrupt signals.

01h: Use Interrupt signal INTA*

02h: Use Interrupt signal INTB*

03h: Use Interrupt signal INTC*

04h: Use Interrupt signal INTD*

05h - FFh: Reserved

It is possible to change this value by software.

When using either the REQ[2]* signal or the PIO signal to report an interrupt to an

external device as the PCI device, please use EEPROM to set the connection with

that device.

7:0

Interrupt Line

Interrupt Line (Initial value: 0x00, R/L)

This is a readable/writable 8-bit register. The software uses this register to indicate

information such as the interrupt signal connection information. Operation of the

TX4925 is not affected.

Figure 10.4.11 PCI Configuration 2 Register

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