CLC031AVEC datasheet(14/31 Pages) NSC

14 / 31 page

Device Operation (Continued)

Figure 4 shows the relationship of clock, data and control

signals for reading Ancillary Data from the port AD[9:0].In

Ancillary Data read mode, 10-bit Ancillary Data is routed

from the Ancillary Data FIFO and read from the port

AD[9:0] at a rate determined by A

CLK.

Ancillary Data read (output) mode is invoked by making the

ANC/CTRL input high and the RD/WR input high. Ancillary

Data is clocked from the FIFO on the L-H transition of A

CLK.

Data may be read from the port on rising edges of A

CLK,

after the specified propagation delay, until the FIFO is emp-

tied. Data may only be read from the port when in the

Ancillary Data mode. Ancillary Data cannot be written to the

port.

To conserve power when the Ancillary Data function is not

being used, the internal Ancillary Data FIFO clock is dis-

abled. This clock must be enabled before Ancillary Data may

be replicated into the FIFO for output. This internal FIFO

clock is controlled by FIFO CLOCK ENABLE, bit-6 of the

ANC 5 register (address 17h). The default condition of FIFO

CLOCK ENABLE is OFF. After enabling the internal FIFO

clock by turning this bit ON, A

CLK must be toggled three (3)

times to propagate the enable to the clock tree.

MULTI-FUNCTION I/O PORT

The multi-function I/O port can be configured to provide

immediate access to many control and indicator functions

that are stored within the CLC031A’s configuration and con-

trol registers. The individual pins comprising this port are

assigned as input or output for selected functions stored in

the control data registers.

The multi-function I/O port is configured by way of an 8x6-bit

through I/O pin 7 CONFIG. The contents of these registers

determine whether the port bits function as inputs or outputs

and to which control function or indicator each port bit is

assigned. Port bits may be assigned to access different

functions and indicators or any or all port bits may be as-

signed to access the same function or indicator (output

mode only). The same indicator or function should not be

assigned to more than one port bit as an input. Controls and

indicators that are accessible by the port and their corre-

sponding selection addresses are given in the I/O Pin Con-

figuration Register Addresses, Table 6. Table 2 gives the

control register bit assignments.

Data resulting from device operation will be sent to the

selected I/O port bit. This same data is also stored in the

configuration and control registers. Mapping the control and

indicator functions in this manner means that device opera-

tion will be immediately reflected at the I/O port pins thereby

ensuring more reliable real-time operation of the device

within and by the host system.

When a multifunction I/O port bit is used as input to a control

clocked into the register bit using A

CLK as shown in Figure 5.

Port timing for bit write operations is the same as for the

ANC/CTRL port operation.

Example: Program multi-function I/O port bit-0 as the CRC

Luma Error bit output.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-low.

Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG

Toggle A

CLK.

Present 310h to AD[9:0] as the register data.

Toggle A

CLK.

EDH/CRC SYSTEM

The CLC031A has EDH and CRC character generation

and checking circuitry. The EDH system functions as de-

scribed in SMPTE Recommended Practice RP-165. The

CRC system functions as specified in SMPTE 292M. The

EDH/CRC polynomial generators/checkers accept paral-

lel data from the de-serializing system and generate the

EDH and CRC check words for comparison with those re-

ceived in the data.

The EDH Enable bit in the control register enables the EDH

generation and checking system. Incoming SDTV data is

checked for errors and the EDH flags are updated automati-

20020111

FIGURE 4. Ancillary Data Read Timing

20020112

FIGURE 5. I/O Port Data Write Timing

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