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PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 3 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Figure 1: PS2500 Block Diagram
Product Description
Serial Interface
The serial interface is a versatile 3-wire interface, Clock (serial clock), Data (serial input) and /CS (chip
select). It enables the PS2500 to operate in a system where one or multiple masters and slaves are present.
To perform a loop-back test at start-up and to check the integrity of the board and processor, the serial data
can be fed back to the master device (for example, MCU/MPU) through a programmable multiplexer. This
facilitates hardware and software debugging.
For more information, see “Serial Interface” on page 5.
Registers
There are ten 16-bit registers in the PS2500. For more information, see “Registers” on page 19 and
“Register Descriptions” on page 19.
Main and Auxiliary
∆Σ Modulators
The PS2500 uses a proprietary (patent pending) configurable 10-bit or 18-bit
∆Σ modulator for the main
synthesizer and 10-bit
∆Σ modulator for the auxiliary synthesizer to provide fractionality.
Modul.data
Main
∆Σ
Main Div.
Modul.Ctl
Ref. Div
SynthCtl
Aux.Div.
Aux.
∆Σ
Registers
Serial
Interface
∆Σ
18-bit
Modulation
Unit
Main
Prescaler
Main
Divider
Main
Phase/Freq.
Reference
Frequency
Fractional
Unit
Detector
and
Charge Pump
Oscillator
Auxiliary
Phase/Freq.
Detector
and
Charge Pump
Reference
Frequency
Dividers
∆Σ
10-bit
Auxiliary
Divider
Fractional
Unit
Auxiliary
Prescaler
Data
Clock
/CS
Fvco_main
/Fvco_main
Fvco_aux
/Fvco_aux
Fref_main
Fref_aux
CP out_aux
LD/PSaux
CPout_main
LD/PSmain
Lock Detection or
Power Steering
Lock Detection or
Power Steering
Fref
Mux_out
Mux
Fpd_main
Fpd_aux
Mod_in
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