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UPD6P5 Datasheet(PDF) 21 Page - Renesas Technology Corp

Part # UPD6P5
Description  MOS INTEGRATED CIRCUIT
PDF  34 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD6P5 Datasheet(HTML) 21 Page - Renesas Technology Corp

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Data Sheet U14760EJ1V0DS00
µPD6P5
AC Programming Characteristics (TA = 25
°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Address setup timeNote 1 (vs. MD0
↓)tAS
2
µs
MD1 setup time (vs. MD0
↓)tM1S
2
µs
Data setup time (vs. MD0
↓)tDS
2
µs
Address hold timeNote 1 (vs. MD0
↑)tAH
2
µs
Data hold time (vs. MD0
↑)tDH
2
µs
MD0
↑→ data output float delay time
tDF
0
130
ns
VPP setup time (vs. MD3
↑)tVPS
2
µs
VDD setup time (vs. MD3
↑)tVDS
2
µs
Initial program pulse width
tPW
0.95
1.0
1.05
ms
Additional program pulse width
tOPW
0.95
21.0
ms
MD0 setup time (vs. MD1
↑)tMOS
2
µs
MD0
↓→ data output delay time
tDV
MD0 = MD1 = VIL
1
µs
MD1 hold time (vs. MD0
↑)tM1H
tM1H + tM1R
≥ 50
µs2
µs
MD1 recovery time (vs. MD0
↓)tM1R
2
µs
Program counter reset time
tPCR
10
µs
CLK input high-, low-level width
tXH, tXL
0.125
µs
CLK input frequency
fX
4.19
MHz
Initial mode set time
tI
2
µs
MD3 setup time (vs. MD1
↑)tM3S
2
µs
MD3 hold time (vs. MD1
↓)tM3H
2
µs
MD3 setup time (vs. MD0
↓)tM3SR
When program memory is read
2
µs
AddressNote 1
→ data output delay time
tDAD
When program memory is read
2
µs
AddressNote 1
→ data output hold time
tHAD
When program memory is read
0
130
ns
MD3 hold time (vs. MD0
↑)tM3HR
When program memory is read
2
µs
MD3
↓→ data output float delay time
tDFR
When program memory is read
2
µs
Reset setup time
tRES
10
µs
Oscillation stabilization wait timeNote 2
tWAIT
2ms
Notes 1. The internal address signal is incremented at the falling edge of the third clock of CLK.
2. Connect a 4 MHz ceramic resonator between the XIN and XOUT pins.



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