Nexperia

74ALVC373

Octal D-type transparent latch; 3-state

-40 °C to +85 °C

Symbol Parameter

Conditions

Min

Typ [1]

Max

Unit

Dn to LE; see Fig. 11

VCC = 1.65 V to 1.95 V

0.8

-0.1

-

ns

VCC = 2.3 V to 2.7 V

0.8

-0.2

-

ns

VCC = 2.7 V

0.8

-0.3

-

ns

th

hold time

VCC = 3.0 V to 3.6 V

0.7

-0.1

-

ns

per latch; VI = GND to VCC; VCC = 3.3 V

[3]

outputs HIGH or LOW state

-

35

-

pF

CPD

power dissipation

capacitance

outputs 3-state

-

14

-

pF

[1] Typical values are measured at Tamb = 25 °C

[2] tpd is the same as tPHL and tPLH.

ten is the same as tPZH and tPZL.

tdis is the same as tPHZ and tPLZ.

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL × VCC 2 × fo) = sum of the outputs

10.1. Waveforms and test circuit

mna884

Dn input

Qn output

tPHL

tPLH

GND

VI

VM

VM

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 8. Input Dn to output Qn propagation delay times

mgu773

LE input

Qn output

tPHL

tPLH

tW

VM

VM

VOH

VI

GND

VOL

VM

VM

VM

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 9. Latch enable (LE) pulse width and latch enable input to output (Qn) propagation delays

74ALVC373

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 3 — 30 April 2021

7 / 15