MCP1641X datasheet(4/44 Pages) MICROCHIP

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MCP1641X

DS20006394D-page 4

 2020-2021 Microchip Technology Inc. and its subsidiaries

Quiescent Current at VIN

IQIN

—4.5

µA

EN = VIN,

PFM mode (MCP16411/3/5/7)

(Notes 2, 4)

Quiescent Current –



Shutdown Mode

IQSHDN

—2.3

3.1

µA

VOUT = EN = GND, 

includes N-Channel and



P-Channel switch leakage

NMOS Switch Leakage

INLK

—85—

Note 5

PMOS Switch Leakage

IPLK

—1—

Note 5

NMOS Switch



On-Resistance

RDS(ON)N

—0.4

—



ISW = 100 mA (Note 4)

PMOS Switch



On-Resistance

RDS(ON)P

—0.5

—



ISW = 100 mA (Note 4)

NMOS Peak Switch



Current Limit

IN(MAX)

0.8

—

Note 4

VOUT Accuracy

VOUT%

—

Includes line and load

regulation, VIN = 1.5V, PWM

Only options

Line Regulation

(VOUT/VOUT)

VDD

—0.1

0.5

%/V

VIN = 1.5V to 2.7V, IOUT = 25 mA,

PWM Only options

Load Regulation

VOUT/VOUT

—0.1

0.2%

IOUT = 10 mA to 100 mA,

VIN = 1.5V, PWM Only options

Maximum Duty Cycle

DCMAX

—90—

Note 4

Switching Frequency

fSW

425

500

575

kHz

IOUT = 100 mA

EN Input Logic High

VIH

——

% of VIN IOUT = 10 mA

EN Input Logic Low

VIL

——

% of VIN IOUT = 10 mA

EN Input Leakage

Current

IENLK

—1—

Note 4

Power Good Threshold

PGTH

—90—

% of VOUT (part of PGT signal)

for MCP16411/2/3/4

Power Good Hysteresis

PGHYS

—5—

% of VOUT

Power Good Delay

PGDELAY

—250

—

µs

Note 4

Power Good Response

PGRESPONSE

—250

—

µs

Note 4

PGT Pin Low-Level

Output

PGTLOW

—0.4

—

ISINK = 2 mA (Note 4)

Low Battery Output Delay

LBODELAY

—150

—

µs

Note 4

Low Battery Output

Response

LBIRESPONSE

—150

—

µs

Note 4

Low Battery Input

Hysteresis

LBIHYS

—20

UVLO pin

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted, VIN = 1.2V, COUT = CIN = 10 µF, L = 4.7 µH, VOUT = 3.3V,

IOUT = 10 mA, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1: For VIN > VOUT, the device enters Automatic Input-to-Output Bypass mode, 

VOUT = VIN – RDS(ON)P * IOUT, maximum VIN is 5.25V.

2: VOUT pin is forced biased with a voltage higher than the nominal VOUT (device is not switching) at

IOUT = 0 mA. IQIN and IQOUT are the device’s current consumption at VIN and VOUT pins during Sleep

periods. The device selects its bias from VIN and/or VOUT.

3: 330

 resistive load, 3.3V VOUT (10 mA).

4: Determined by characterization, not production tested.

5: This is ensured by design.

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