UPD6P9 datasheet(16/73 Pages) RENESAS

16 / 73 page

µPD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3. PORT REGISTERS (PX)

The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers.

After reset, the port register values are as shown below.

Figure 3-1. Port Register Configuration

Notes 1.

×: Refers to the value based on the KI and S2 pin state.

×: Refers to the value based on decrease of power supply voltage (0 when VDD ≤ VID)

Remark VID: RAM retention detection voltage

Table 3-1. Relationship Between Ports and Reading/Writing

Port Name

Input Mode

Output Mode

Read

Write

Read

Write

KI/O

Pin state

Output latch

Pin state

—

Pin state

—

Note

—

S1/LED

Pin state

—

Pin state

—

Pin state

—

Note When in OFF mode, “1” is always read.

Port register

KI/O7

P00

After reset

FFH

KI/O6

KI/O5

KI/O4

KI/O3

KI/O2

KI/O1

KI/O0

P10

KI3

P01

××××11×1BNote 1

KI2

KI1

KI0

S1/LED

P11

P3 (control register 0)

DP11

P03

0000

×000BNote 2

DP10

DP9

DP8

RAM

retention

flag

–ID1

ID0

P13

P4 (control register 1)

P04

26H

Pull-down

S0/S1

Pull-down

STOP release

S1/LED mode

KI/O mode

S0 mode

P14

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