µPD6379, 6379A, 6379L, 6379AL

11

Data Sheet S11588EJ5V0DS

•

If the clock is also supplied to CLK while data is not sampled (refer to Fig. 4-1), make sure that the changing

timing of LRCK coincides with the falling edge (point A) of CLK after the LSB has been input.

Fig. 4-1 Input Timing Chart (1)

•

If the clock is supplied to CLK only while data is sampled (refer to Fig. 4-2), set the changing timing of LRCK

in between the falling edge (point A) of CLK after the LSB has been input and the start of inputting the next

MSB (point B) (points A and B are included).

Fig. 4-2 Input Timing Chart (2)

16

Invalid

Invalid

LSB

CLK

SI

123456789 10 11 12 13 14 15 16

1

2

3

4

LRCK

MSB

LSB

MSB

A

A

1 sample data period

16

Invalid

Invalid

LSB

CLK

SI

123456789 10 11 12 13 14 15 16

1

2

3

4

LRCK

MSB

LSB

MSB

A

A

B

B

1 sample data period

Changing period of LRCK

Changing period of LRCK