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UPD7225 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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UPD7225 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 50 page  Data Sheet S14308EJ6V1DS 37 µµµµPD7225 DC Characteristics (TA = −−−−10 to +70 °°°°C, VDD = 5 V ±±±± 10%) Item Symbol Condition MIN. TYP. MAX. Unit High level input voltage VIH 0.7 VDD VDD V Low level input voltage VIL 0 0.3 VDD V High level output voltage VOH /SYNC, /BUSY, IOH = −10 µAVDD − 0.5 V Low level output voltage VOL1 /BUSY, IOL = 100 µA0.5 V VOL2 /SYNC, IOL = 900 µA1.0 V Output short-circuit current IOS /SYNC, VO = 1 V −300 µA High level input leakage current ILIH VI = VDD 2 µA Low level input leakage current ILIL VI = 0 V −2 µA High level output leakage current ILOH VO = VDD 2 µA Low level output leakage current ILOL VO = 0 V −2 µA Common output impedance RCOM COM0 to COM3 Note 1, VDD ≥ VLCD 57 k Ω Segment output impedance RSEG S0 to S31 Note 1, VDD ≥ VLCD 714 k Ω Power supply voltage IDD CL1 external clock, fC = 200 kHz Note 2 100 250 µA Notes 1. Applies to Static, 1/2 bias, 1/3 bias 2. Abnormal current will flow if the external clock supply is removed. DC Characteristics (TA = 0 to +70 °°°°C, VDD = 2.7 to 5.5 V) Item Symbol Condition MIN. TYP. MAX. Units High level input voltage VIH1 Except /SCK 0.7 VDD VDD V VIH2 /SCK 0.8 VDD VDD V Low level input voltage VIL1 Except /SCK 0 0.3 VDD V VIL2 /SCK 0 0.2 VDD V High level output voltage VOH /SYNC, /BUSY, IOH = −7 µAVDD − 0.75 V Low level output voltage VOL1 /BUSY, IOL = 100 µA0.5 V VOL2 /SYNC, IOL = 400 µA0.5 V Output short-circuit current IOS /SYNC, VO = 0.5 V −200 µA High level input leakage current ILIH VI = VDD 2 µA Low level input leakage current ILIL VI = 0 V −2 µA High level output leakage current ILOH VO = VDD 2 µA Low level output leakage current ILOL VO = 0 V −2 µA Common output impedance RCOM COM0 to COM3 Note 1, VDD ≥ VLCD 6k Ω Segment output impedance RSEG S0 to S31 Note 1, VDD ≥ VLCD 12 k Ω Power supply voltage IDD CL external clock, VDD = 3 V ± 10%, fC = 140 kHz Note 2 30 100 µA Notes 1. Applies to Static and 1/3 bias 2. Abnormal current will flow if the external clock supply is removed. |
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