UPD7566ACS datasheet(21/60 Pages) RENESAS

21 / 60 page

µPD7566A, 7566A(A)

2.9

SYSTEM CLOCK GENERATOR

The system clock generator consists of a ceramic oscillator, a 1/2 frequency divider, standby mode (STOP/HALT)

control circuit, and other circuits.

The ceramic oscillator can oscillate, when an external ceramic oscillator is connected across pins CL1 and CL2.

The signal output by the internal ceramic oscillator is a system clock (CL), which is then divided in two to create

a CPU clock (ø).

The standby mode control circuit mainly consists of a STOP flip-flop and HALT flip-flop.

The STOP flip-flop is set by a STOP instruction, stopping the clock supply. When the ceramic oscillator is

operating, this flip-flop stops the oscillator, setting the microcomputer in the STOP mode.

The STOP flip-flop is reset when a high-level RESET signal is input. As a result, the ceramic oscillator resumes

its operation, and the clocks supply is started, when the RESET signal later goes low.

The HALT flip-flop is set by a HALT instruction, disabling the input of the 1/2 frequency divider, which generates

CPU clock ø, and thereby stopping only CPU clock ø (HALT mode).

The HALT flip-flop is reset by the HALT RELEASE or the falling of RESET input (which becomes active when one

of the test request flags has been set), allowing the supply of ø to be started.

The HALT flip-flop remains set even while the RESET signal is active (high-level), and operates in the same

manner as in the HALT mode.

When Power-ON Reset is performed, the ceramic oscillator starts at the rising edge of the RESET signal. After

the oscillator has started, however, a specific period is required for the oscillator to stabilize. To present the CPU

from malfunctioning due to anstable clock, the HALT flip-flop is set to suppress the CPU clock ø while the RESET

signal is high. Therefore, the high-level width of the RESET signal must be greater than the time required for the

ceramic oscillator you use to stabilize.

Fig. 2-9 System Clock Generator

Note

indicates that an instruction has been executed.

CL1

CL2

Ceramic

oscillator

Oscillation

stops

STOP F/F

HALT F/F

1/2

STOP

HALT

RESET (high)

HALT RELEASE

RESET (

)

RESET (

)

ø (to CPU)

CL (System clock)

Note

UPD7566ACS Datasheet(PDF) 21 Page - Renesas Technology Corp

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